The present invention relates to a microcomputer having a CPU (central processing unit) and a nonvolatile memory capable of being electrically written and erased, and relates in particular to a technology effective on one-chip microcomputers having flash memories for permitting or prohibiting programming and erasure on nonvolatile memories.
Electrically erasable and programmable nonvolatile memories such as flash memories, store information according to differences in threshold voltages programmed into the memory cells. This differential in threshold voltages in the flash memory is implemented by differences in the amount of electrons and positive holes stored by the floating gates. For example, applying a voltage at a high level relative to a threshold voltage in a stable thermal state is called the program status; and applying a voltage at a low level relative to the threshold voltage is called the erase status (The reverse of this definition may also be true.) There are no particular restrictions at this time but the erase operation to set the memory cell to erase status and the programming operation to set the memory cell to program status involve repeatedly applying a high voltage pulse and verifying the resulting threshold voltage. The writer mode and the boot mode are operating modes to allow programming and erasing the on-chip flash memory of the microcomputer. The writer mode is an operating mode treating the microcomputer as equivalent to a flash memory chip to program and erase the memory by connecting to a programming device such as an EEPROM writer. The boot mode is an operating mode for example, to establish communications to allow programming or erase with the microcomputer installed the system, by way of synchronized start-stop or a nonsynchronized serial interface (UART). The writer mode can be utilized to program data or program in an initialized state on the on-chip memory, prior to installation in the system. The boot mode on the other hand, can be utilized to reprogram information stored in the on-chip flash memory for program version upgrades or tuning data, prior to installation in the system.
The boot mode of the related art utilizes a serial interface as the basic interfacing method so a serial interface circuit such as for start-stop synchronizing, was incorporated into the system board of the microcomputer, when doing on-board programming by using the boot mode.
However, some systems essentially do not use start-stop synchronization. In disk drive systems such as CD-ROM (Compact Disk Read Only Memory), CD-RW (Compact Disk Rewritable), DVD-ROM (Digital Video Disk Read Only Memory), DVD-RAM (Digital Video Disk Random Access Memory) an interface such as an ATAPI (AT Attachment Packet Interface) or SCSI (Small Computer System Interface) is required. An area network interface called HCAN is used in automobile control systems such as for engines and transmissions. Even if the user""s system board had interfaces such as ATAPI, SCSI or HCAN, if a serial interface for start-stop synchronizing was also required for on-board programming in boot mode, this created the problem of overhead costs in the user""s system board.
This problem could be avoided by on-board programming in a memory storage area (in other words, user memory area) on an area of the flash memory where programming is freely allowed, in a user program mode capable of running programs. In other words, programming in advance, in writer mode, a dedicated user board communications protocol program such as for ATAPI in the user memory area. After programming this program, the microcomputer is mounted in the user""s system board, and if that dedicated user board communications protocol program is then run by the CPU, the user memory area can be programmed with program version upgrades and data tuning performed.
However, when the dedicated user board communications protocol program was also written on the user area along with the user control program and tuning data, the user had to make it difficult to accidentally erase this dedicated user board communications protocol program, placing the large burden on the user of having to write a program. Further, when the CPU ran out of control in user program mode after installing the microcomputer in the system, and the processing program for running the communications protocol in user program mode was accidentally erased, there was no longer any chance of establishing an interface with the user system board for programming and erasing. Unless the microcomputer chip was removed, and the writer mode used, this method had the problem as clearly stated by the inventor himself, that programming could not be performed. In the specifications of the present invention, the term user broadly signifies the user of the semiconductor device such as the microcomputer. Therefore, if the manufacturer of the semiconductor device utilizes that semiconductor device in some manner, then that manufacturer is by definition a user.
The present invention therefore has the object of providing a microcomputer not prone to lose program information from the nonvolatile memory such as having communication protocols with the mounted board in the event the system is subjected to fatal errors such as deletion.
Another object of the present invention is to provide a microcomputer capable of ensuring an interface can be established with the microcomputer board separately supporting the communication protocol.
Yet, another object is to provide a microcomputer capable of preventing loss of stored information from the on-chip nonvolatile memory even if the CPU is running out of control.
The above described and other objects and unique features will become clear from the description of the present invention with reference to the accompanying drawings.
[1] An overview of a typical aspect of the invention as disclosed in these specifications is disclosed briefly as follows.
Besides a third area (user mat) for programming items such as a user (microcomputer user) control program, a second area (user boot mat) is provided in the on-chip nonvolatile memory of the microcomputer. This user boot mat is used as a memory storage area for programming for example, dedicated user communication protocols, and this mode also provides a user boot mode as a dedicated mode for running the program. This user boot mode is not capable of programming and erasing the user boot mat.
The effects rendered are as follows. (1) The microcomputer can make use of its own optional interface since a user boot mat capable of storing a dedicated user communication protocol is provided. (2) A serial interface need not always be provided on the user mounted board since an interface selected by the user can utilized to program and erase the nonvolatile memory. (3) A user optional program interface for programming and erasing can be implemented by separating the user boot mat and the user mat so that a control program for storage and use in the user mat can easily be made, even without programming a dedicated communication protocol program in the user mat. In other words, special measures for preventing erasure of the communications control program used in the user program mode are not needed. (4) The user boot mode started up from the user boot mat, is unable to program on or erase the user boot mat, so that information stored in the boot mat is not destroyed even when the system is running out of control, and even if the CPU runs out of control during debugging, damage will not extend to the program controlling the external interface so that the user mat can be freely programmed on-board the chip, without having to remove the microcomputer chip.
[2] A microcomputer of a detailed first aspect of the present invention includes a CPU, a nonvolatile memory having an electrically erasable and writable first area (boot mat), a second area (user boot mat) and a third area (user mat), and an operating mode specifier means. The operating mode specifier means specifies a first mode (boot mode) for processing the program on the first area in the CPU and disabling programming and erasing on the first area; a second mode (user boot mode) for processing the program on the second area in the CPU and disabling programming and erasing on the first area and second area; and a third mode (user mode) for processing the program on the third area of the CPU and disabling programming and erasing on the first area and second area; and implements the above for example by the mode signal input circuits.
A microcomputer in this state signifies a condition where a specific program is not stored in the second area and third area, in other words, a state prior to the user storing the desired program in the second and third areas.
When the microcomputer is mounted in the system board, a communication protocol program for establishing the characteristic interface in the system board is stored in the second area, and tuning data and a user program for controlling the system board are stored in the third area, and utilized for controlling the user system. To perform on-board programming, a second mode such as user boot mode is specified, the communications protocol program of the second area is processed in the CPU, the characteristic interface established on the system board, the user program version of the third area is upgraded, or the tuning data is programmed. Therefore, the above effects in (1) through (4) are rendered.
[3] A microcomputer of a detailed second aspect of the present invention includes a CPU, a nonvolatile memory having an electrically erasable and writable first area (boot mat), a second area (user boot mat) and a third area (user mat), and an operating mode specifier means for selectively specifying the first mode, second mode or third mode. The CPU processes the program of the first area by specifying the first mode, processes the program of the second area by specifying the second mode, and processes the program of the third area by specifying the third mode. In the nonvolatile memory, specifying the first mode enables programming and erasing on the second area and third area, and disables programming and erasing on the first area; specifying the second mode enables programming and erasing on the third area and disables programming and erasing on the first area and second area; specifying the third mode enables programming and erasing on the third area and disables programming and erasing on the first and second area. This microcomputer therefore renders the above effects of (1) through (4).
The first area may contain a first communications control program to establish an external interface with the microcomputer. Since programming and erasing are disabled in operating modes for both the first area and second area, initial values can be written using a programming device such as an EPROM writer in the semiconductor manufacturing process. The first communication control program may be a serial interface program functioning by basic start-stop synchronization.
The second area may contain a first communications control program to establish an external interface with the microcomputer. Since programming and erasing in the second area are enabled in the first mode, the second communication control program may be a dedicated user communications protocol, or in other words, may be a communication control program that satisfies the characteristic interface specifications (for example, ATAPI) of the system board.
Since programming and erasing in the first area are disabled in all of the first through third operating modes, placing an erase and programming program in the first area of the nonvolatile memory will prevent unforeseen loss.
A transfer (control) program for the erase and programming program may be installed in the same way, in the second area.
The RAM, on which the CPU may perform transfer processing to transfer the erase and programming program, may be built in the microcomputer. The CPU can run the erase and programming program on the built-in RAM.
In view of the need to prevent programming of the nonvolatile memory that occurs when the CPU runs out of control, a command specifying programming operation may be applied to the nonvolatile memory from an external terminal (separate from the mode specifier means), as a necessary condition for enabling erase and programming operation.
[4] In the microcomputer of the second aspect of the invention, examination of the CPU reset vector address (vector address checked after canceling reset) shows that the lead (beginning) addresses of the first area, second area and third area are set as companion addresses in the address space in the CPU, and a first register means (FMATS) for exclusively specifying the second area or the third area as the lead address utilized by the CPU, is installed in the CPU address space.
In this configuration, when the program of the first area is executed by specifying the first mode, erasing and programming cannot be performed on the first area unless the program of the first area itself includes a routine for programming and erasing on the first area. If assumed that the microcomputer manufacturer will develop and write the program for storage in the first area, then the disabling of programming and erasing operation on the first area is virtually assured. After running the program for the first area specified by the first mode, a shift to the second area or third area program can be made according to the setting on the first register means. After this, returning the first area program to a state where it can again be executed is basically impossible just by using the programs stored in the second area or the third area. Even if the hardware allows returning to that state, erasing and programming on the first area is impossible.
When a RAM is installed in the CPU address space, the CPU can load and run programs from the RAM.
If changing the settings on the first register means is allowed, as a condition for the CPU to process programs on the RAM, a smooth transition can be made from fetching of a program from any of the first through third areas to executing the program in a separate area. Making changes to the first register setting may be allowed under the condition that the bus control means (BSC) detects the processing of the program on the RAM by the CPU.
Installing a second register means (FKEY) set with information allowing an operation to store the erase and programming program in the RAM, and resetting this second register means information by the nonvolatile memory can be made a required condition for allowing erasing and programming. Therefore, even assuming the CPU runs out of control at a time that transferring the erase and programming program to the RAM is not required, the probability is reduced that the erase and programming program will be mistakenly transferred to the RAM and executed due to resetting of the second register means. Further, even assuming the CPU runs out of control when transferring the erase and programming program to the RAM, the second register means is set to a status inhibiting erasing and programming so that the probability of the erase and programming program being mistakenly executed at this time can be lowered.
[5] In the erase and programming program for the microcomputer of the second aspect of the invention, a RAM is installed in the address space of the CPU and the erase and programming program is stored in the first area, and the CPU transfers the erase and programming program to the RAM in response to the first mode, and fetches the erase and programming program from the transfer destination RAM. There is no need for the microcomputer user to develop an erase and programming program. If the erase and programming program on the RAM is executed, then the erase and programming on the second and third areas in first mode will proceed smoothly.
To also utilize the erase and programming program of the first area, in the second mode, the CPU may for example, in second mode, switch to processing the first area program in response to a first setting value of the third register means (SCO), and transfer the erase and programming program to the RAM, and restore status to processing the program of the second area.
To also utilize the erase and programming program of the first area, in the third mode, the CPU may for example, in third mode, switch to processing the first area program in response to a first setting value of the third register means (SCO), and transfer the erase and programming program to the RAM, and restore status to processing the program of the third area.
Installing a second register means (FKEY) set with a second setting value allowing operation to store the erase and programming program in the RAM, and resetting the third setting value with this information can be made a necessary condition for erasing and programming. A state where a second setting value is set in the second register means may be made a necessary condition for allowing setting of the first setting value in the third register means. In other words, the probability of destroying the user program increases, when the program runs out of control and the erase and programming program is transferred at a point when the user does not any erasing or programming. Therefore, to avoid this problem, the user stores a second setting value in the second register means, prior to setting the first setting value in the third register means. The first setting value cannot be set in the third register means when the second setting value has not been stored. When the second setting value has been stored in the second register means, the first setting value can be set in the third register means and in this way allow transferring the program.
The second register is used in view of the case where the program runs out of control after the erase and programming program has been transferred. Basically, due to other conditions, erasing and programming will not be performed even if the CPU runs out of control. However, to increase the reliability even further, the user sets the third setting value in the second register means, prior to erasing or programming. When this third setting has not been stored, erasing and programming is still impossible even if other conditions for erase and programming have been enabled by accident.
[6] The memory storage area available to the user in the non-volatile memory is as follows. The microcomputer includes a CPU, and a nonvolatile memory capable of being electrically erased and programmed, and the nonvolatile memory includes a first memory mat (user boot mat) and a second memory mat (user mat); and the first memory mat and second memory mat are capable of being exclusively selected in the register, and when the first memory mat is selected, erasing and programming is disabled on the first memory mat; and when the second memory mat is selected, erasing and programming is disabled under the condition that shifting of the program to execute status on the RAM is canceled. Unexpected problems occurring due to erasing or programming on the memory mat whose program is currently being run are therefore prevented.
[7] The overall memory storage area of the nonvolatile memory is as follows. The microcomputer includes a CPU, and a nonvolatile memory capable of being electrically erased and programmed, the nonvolatile memory includes a first area (boot mat) having a communications control program (serial communications control program PGM) for establishing an external interface with the nonvolatile memory; and a second area (user boot mat) capable of being erased and programmed via an external interface established by a communications control program processing by the CPU; and a third area (user mat) capable of being erased and programmed via an external interface established by a communications control program processing by the CPU and also of being erased and programmed by the CPU with the second area program.
[8] In another aspect of a microcomputer for mounting with a board having a first interface (ATAPI, SCSI, HCAN), the microcomputer has a central processing unit, and a nonvolatile memory having a first memory storage area (boot mat) for storing a first communications program for establishing a communications protocol (UART) utilizing a second interface (SCI) different from the first interface; a second memory storage area (user boot mat) for storing a second communication program for establishing a communications protocol using the first interface; and a third memory storage area (user mat) stored with a control program executed by the central processing unit in the specified first operating mode.
The first memory storage area further stores a communications program, and the second communications program stored at this time in the second memory storage area, is written in the second memory storage area in the first programming mode executed by the central processing unit running the programming program and the first communications program.
The control program stored in the third memory storage area is written into the third memory storage area by either a first programming mode, or a second programming mode executed by the central processing unit running the programming program and the second communications program stored in the first memory storage area.
The first memory storage area further stores an erase program, and the second communications program stored at this time in the second memory storage area, can be erased from the second memory storage area in the first erase mode executed by the central processing unit running the programming program and the first erase program.
The control program stored in the third memory storage area can be erased from the third memory storage area in either a first erase mode, or a second erase mode executed by the central processing unit running the second communications program and the erase program stored in the first memory storage area.
A microcomputer of yet another aspect of the invention is comprised of a central processing unit, and nonvolatile memory having a first memory storage area for storing a communications program and a first communications program for establishing a communications protocol (UART) utilizing a first interface (SCSI); a second memory storage area for storing a second communications program to establish a communications protocol utilizing a second interface (ATAPI, SCSI, HCAN) different from the first interface, and a third memory storage area storing a control program executed by the central processing unit in a specified first operating mode.